1. Field of the Invention
The present invention relates to a semiconductor device that performs high-speed access by dividing a memory cell array into a plurality of banks in which memory cells mutually operate independently.
Priority is claimed on Japanese Patent Application No. 2007-171979, filed Jun. 29, 2007, the content of which is incorporated herein by reference.
2. Description of Related Art
In recent years, a dynamic random access memory (DRAM) has seen advances in terms of higher capacities, higher speeds, and lower power consumption. In particular, there has been intense demand for higher data transfer speeds, leading to the proposal of new architectures such as double data rate (DDR), DDR-II and DDR-III. Under this environment, shortening the column cycle that determines the operation speed in the memory is a key point for offering high-speed DRAM.
Referring to FIG. 9, the constitution of this kind of DRAM shall be described. FIG. 9 is an example of a block diagram that shows the constitution of a 1-Gbit DDR-II Synchronous Dynamic Random Access Memory (SDRAM). This SDRAM has a known structure including a memory cell array (MCA) 8 which consists of a plurality of memory cells, a row address buffer (XAB), a column address buffer (YAB), a row decoder (XDEC) 6, and a column decoder (YDEC) 5 for specifying addresses of the memory cell array 8, column selecting lines (YS) 7, column selecting switches (YSW) 80, sense amplifiers (SA) for reading and writing data, a main amplifier (MA), an output buffer (DOB), an input buffer (DIB), control signal buffers (RB, CB and WB), and an internal voltage generating circuit (VG). These components are constructed on a single semiconductor chip by the known semiconductor fabrication technology.
In operation, the address signal Ai is supplied from an external source to the DRAM, and the row address buffer XAB and the column address buffer YAB generate a row address signal and a column address signal, respectively. The row address signal and the column address signal are applied respectively to the row decoder 6 and the column decoder 5, which select a desired memory cell in the memory cell array 8.
The column decoder 5 activates the YS signal 7 that is a column selecting line corresponding to the input column address. By turning ON the corresponding column selecting switch 80, the column selecting line 7 that is activated by the column decoder 5 controls the connection of a bit line to a local I/O line (LIO).
In a data reading mode, data is sent through a sense amplifier 20, a local I/O line LIO, a main I/O line MIO, a sub-amplifier, and the main amplifier MA to a read/write bus RWBS, from which output data Dout is output through the output buffer DOB. In the dcta writing mode, the input data Din is input from an input buffer DIB.
Moreover, control signals for the DRAM include a row address strobe signal RAS, a column address strobe signal CAS, a write enable signal WE and the like that are supplied from an external source through respective buffers RB, CB and WB to the DRAM. Based on the supplied control signals, a control circuit (identical to the control circuit in the present embodiment) generates internal control signals which control operation of internal circuits of the DRAM.
The DRAM has an internal power supply system including an internal voltage generating circuit VG which generates various internal voltage levels including a substrate potential, a step-up power supply potential, and a step-down power supply potential in response to the external power supply potential VDD and the ground potential VSS that are applied from an external source to the internal voltage generating circuit VG The generated internal voltage levels are applied to internal circuits including the memory cell array MCA 8 and peripheral circuits thereof.
FIG. 10 of the accompanying drawing shows a conventional structure of the memory cell array 8 shown in FIG. 9. FIG. 10 shows a circuit arrangement of two mats divided from a single bank. To these mats, there are connected the column selecting line YS 7 from the column decoder 5, mat activating signals (RCSEQB) 50 from the row decoder 6, and sub-word lines SWL. The mat activating signals 50 activate the mats, which are units further dividing a bank. Each of the mat activating signals 50 is connected to an inverter 30 which outputs a signal having a logic level inverted from the mat activating signal 50, as bit line precharging signal (BLEQT) 40. The bit line precharging signal 40 is a control signal for precharging bit lines (BLT and BLB) and controlling common sources in sense amplifiers 201 and 202. For stopping precharging of the bit lines, the bit line precharging signal 40 goes low in level (“L” level).
The sense amplifiers 201 and 202 amplify data that are read to bit lines BLT and BLB. Column selecting switches (YSW) 801 through 804 are provided between the sense amplifiers 201 and 202 and local I/O lines LIO, and are controlled by the column selecting lines YS 7.
Operation of the memory cell array shown in FIG. 10 shall be described below. It is assumed that data is read from a cell in a left-side mat of the two mats shown in FIG. 10.
First, when an ACT command for selecting a row address is input, one mat activating signal RCSEQB 50 is selected from the bank address and the row address (XA), making the mat activating signal high in level (“H” level). The bit line precharging signal BLEQT 40 output from inverter circuit 30 goes low in level, allowing a memory cell signal to be read.
Next, when a READ command is then input, one column selecting line 7 is selected by the column decoder 5. Four column selecting switches 801 through 804 which are connected to the selected column selecting line 7 are then turned ON, and bit line pair BLT and BLB data are amplified by the sense amplifiers 201 and 202 and read to the local I/O lines LIO.
A data input/output line pair IOT and IOB is connected to a data amplifier as shown in FIG. 11. The data that is amplified by this data amplifier is output to an output buffer.
With the memory cell of the conventional semiconductor devlce shown in FIG. 10, all four column selecting switches 801 through 804 which are connected to one column selecting line 7 are simultaneously activated. Therefore, if the number of mats controlled by one column selecting line 7 increases, the number of column selecting transistors connected to that one column selecting line 7 also increases. For that reason, the burden on the column selecting line 7 increases, and signal delay becomes a problem.
In the conventional semiconductor device described above, the column selecting switches that are connected to one column selecting line are simultaneously activated. In this way, when the bit lines are divided into a greater number of bit lines, the number of column selecting switches that have to be energized by a single column selecting line YS increases. For this reason, the burden on the column selecting line YS further increases, and the signal delay becomes greater.
In order to solve this problem, assuming a constitution of bit lines, local data I/O lines that bundle these bit lines, and data I/O lines that bundle these local data I/O lines, there is a constitution that reduces the number of selecting switches that respectively select them, reduces the burden on the selecting line that controls each selecting switch, and reduces the signal delay amount (for example, refer to Japanese Unexamined Patent Application, First Publication, No. 2006-134469)
The semiconductor device of the abovedescribed JP 2006-134469 A can reduce the signal delay that controls the selecting switches by lowering the load on the selecting line. However, since the precharging of the data I/O lines cannot be performed until outputting from the data amplifier DAMP to the data latch of the next stage, there is the shortcoming of a delay occurring in the reading of data.
That is, in the conventional example described above, in the constitution in which each bit line, local I/O lines and data I/O lines are connected as shown in FIG. 10, and the data I/O line and data amplifier are connected as shown in FIG. 11, it is necessary to perform precharging of the data I/O line and the data amplifier simultaneously as shown in FIG. 12. However, in the state of outputting data to the output buffer 75, it is not possible to perform precharging of the data I/O line that has already completed the process of transmitting data to the data amplifier. Therefore, precharging of the data I/O line pair 60 and the data amplifier 70 are performed with a signal that deactivates the data amplifier 70. For this reason, precharge processing of the data I/O line pair 60 for reading the next data is delayed, and the speeding up of the read cycle is limited.
In recent years, even in a semiconductor device of low power driving, improvement of the data transfer rate has been desired.
As the bit number configuration that is the data-read unit in a semiconductor device has increased from ×16 to ×32 to ×64, the spread in operation speed of the precharge of data I/O lines has become two times, four times, eight times. Due to setting the precharge time at the slowest precharge rate, this spread affects the data read operation speed.
As shown in the timing chart of FIG. 12, in the case of the precharge of the data I/O line not finishing even if the data amplifier is enabled, amplification of the differential voltage of the data I/O line pair is performed in the data amplifier prior to the precharging completely finishing due to the delay of the precharge operation of this data I/O line. For this reason, due to a reduction in the differential voltage of the data I/O line pair during driving of the data amplifier, a speed reduction in the amplification operation of the data amplifier results, serving as a cause of rate limit of the data read clock cycle.
Moreover, due to the differential voltage of the I/O data line pair prior to precharge, the previous differential voltage is not completely dissolved, and so may lead to a malfunction of outputting data that differs from the actual data.
FIG. 13 shows a circuit configuration of the writing amplifier. FIG. 14 shows the timing chart during writing of data. Prior to the state of the write amplifier being enabled, precharge of the data I/O line is performed. Similarly to in the read mode, at the point in which the write amplifier has been enabled, precharging has not been completely completed, which may cause a reduction in the writing sneed.
Y switching signals YS0, YS1, YS2, and YS3 that turn the Y switch YSW 80 ON/OFF are output from a control circuit not illustrated in sequence based on an external clock CLK that is supplied from an external source, and a CASB and column address. The speed of the read operation and write operation are determined by the abovementioned external clock CLK.
In order to solve the abovementioned problem, there is known a method of reducing the precharge time of the data I/O line by increasing the voltage of the power supply for precharging and raising the precharge current. However, since low power consumption of the semiconductor device is required, a means of increasing consumption current is not adopted.